#Encoder decoder multiplexer demultiplexer

[jnthn2rris]

https://www.futureelectronics.com/p/semiconductors--analog--multiplexer-demultiplexer/dg406dn-t1-e3-vishay-3148293

What is an encoder and a decoder, digital data converter, communication network

Single 16 Channel 5 to 20 V 50 Ω CMOS Analog Multiplexer - PLCC-28

[electronicsexplained]

Let's dive into the basics of digital systems! Here's a quick overview:

Digital Systems Fundamentals

Binary Numbers: Digital systems operate on binary numbers, which use only two digits, 0 and 1. Each binary digit is called a bit. Larger numbers are represented by combining multiple bits.

Logic Gates: These are the building blocks of digital systems. Common logic gates include AND, OR, NOT, NAND, NOR, XOR, and XNOR. Each gate performs a specific logical operation on one or more input signals to produce an output signal.

Combinational Logic Circuits: These circuits output results based solely on the current inputs, without involving any memory elements. Examples include adders, multiplexers, decoders, and encoders.

Sequential Logic Circuits: Unlike combinational circuits, sequential circuits have memory elements (like flip-flops) and their output depends on both the current inputs and previous states. Examples include counters, shift registers, and finite state machines.

Flip-Flops and Latches: These are basic memory elements used in sequential circuits. Flip-flops store a single bit of data and change state based on clock signals. Common types include SR, D, JK, and T flip-flops.

Registers: A collection of flip-flops used to store multi-bit values. Registers are essential for storing intermediate data during processing.

Counters: Special types of registers that go through a predetermined sequence of states. They can count up, count down, or count in a specific pattern.

Multiplexers (MUX) and Demultiplexers (DEMUX): Multiplexers select one of many inputs to pass to the output based on control signals. Demultiplexers do the opposite, taking one input and routing it to one of many outputs.

Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC): These devices convert analog signals to digital form and vice versa. AD converters sample analog signals and represent them as binary numbers, while DA converters do the reverse.

Why They Matter

Understanding digital systems is fundamental for designing and working with any kind of electronic device. Whether it's computers, smartphones, or embedded systems, the principles of digital logic underpin their operation.

Do you have any specific topics you want to explore further?

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Application of multiplexer, decoder, decoder circuit, digital logic

Single 16 Channel 5 to 20 V 50 Ω CMOS Analog Multiplexer - PLCC-28

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[networkeducative]

OSI Model

OSI Model

OSI Model stands for the Open System Interconnection Model. This model is the model that was published by the ISO "International organization for Standardization" in the 1984. This Model is published just for communication purposes of the different vendors. There were the different devices that manufacturing were different and their pattern of the commination mismatch to each other. So OSI model published for the communication of the different vendors because it is open source so that is the reason this model called the

Open System Interconnection Model.

This Model is known as the theoretical model. This model is classify into the seven layers just for the easy understanding of the networking how the data propagate from sender to the receiver. So following are the seven layers of Open System Interconnection Model:

Fig: OSI Model

Application Layer  

Presentation Layer

Session Layer

Transport Layer

Network Layer

Data Link Layer

Physical layer

Application Layer  

Application layer is the 7th layer of the OSI Model and if we start the  top to bottom then then it will make the 1st layer. So the mainly sequence that mostly common is bottom to top. Application layer is the layer that provide the user interface for user to interact. There are many applications in the computer field and if we see applications are divided into the two types: 1)Computer Application 2)Network Application. We need the network application for the communication and communication is necessary for the resources sharing. There are the multiple protocols that operate on this layer that are the following:

Http that use the port number 80.

Https that   use the port number 443.

FTP that use the port number 20-21.

SSH that use the port number 22.

Telnet that use the port number 23.

SMTP that use the port number 25.

TFTP that use the port number 69.

Presentation Layer

Presentation layer is the layer that is the 6th layer of the OSI model and this layer concerns with the presentation of the data. presentation layer is the layer at which encoding of the data and decoding of the data  occur and that layers also concerns with the encryption and decryption of the data. Compression and decompression of the data also a part of the presentation layer .

Session Layer

Session layer is the 5th layer of the OSI model and that layer is play an important role for the checking the availability of the destination. That layer is very important layer which is use to establish  the session, maintain the session, and the terminating of  session. The other main role of this layer is data synchronization of the session streams that are the multiple. This layer work as the dialog controller. This layer is the layer that can directly communicate with presentation layer and the transport layer.

Transport Layer

Transport layer is the layer that is known as the 4th layer of the Open Systems Interconnection Model. This is the layer that concern with the identifying of the service. The main functionality of this layer is Multiplexing and Demultiplexing. The process of segmentation of data   also concerns with that layer. Sequencing and reassembling of the data happen on that layer. Flow Control and error correction are  also occurring on that layer. TCP transmission control protocol and UDP user datagram protocol work on this layer.

TCP {Reliable, Connection Oriented, Slower than UDP}

UDP{Unreliable, Connectionless, Faster}

Network Layer

Network layer is the 3rd layer of the OSI model and that layer is most common and important layer of the OSI model. That layer is the layer on which our most important and effective device router works. Network layer is the layer that concern with the following :

Logical Addressing

Path Determination

Routing Protocols{RIP, RIPv2, OSPF, BGP, EIGRP}

Routed Protocols {IP, IPX, AppleTalk}

Datalink link Layer

Datalink link layer is the 2nd layer of the OSI model and here switch that is the networking device operate on this layer. Data link layer is the layer that concerns with the local delivery of the frames in between the devices. Here we see the most important protocols that are the following :

HDLC

HDLC stands for the Higher Level Datalink Control Protocol.

Cisco Proprietary.

No support Authentication, compression, and error correction.

PPP

PPP stands for the point to point protocol.

Standard Protocol.

Support Authentication, compression, and error correction.

Physical layer

This layer is the first layer of the OSI model. Physical layer is the layer that concern with the bits transfer of the from one medium to other medium. Hybrid Universal Broadcast device is the device that work on that layer. This layer concerning with how the bit converted into the signals.

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VHDL VS VERILOG

The comments all include links to other websites or publications. Let me first create the answer story. After reading this response, one should clearly understand Verilog HDL and where they stand in the learning process.

Verilog is not a programming language. It isn't used in any platform for development reasons, and it doesn't make programming easier (relating to scripting). It does not create an environment or user interface that is interesting.

Verilog coding builds a digital circuit for a behavioural purpose while simultaneously modelling it, resulting in digital circuits. Before moving on to Verilog, make sure the digital circuit is in your blood and not in your heart. It breaks and also fails!

How should you proceed with digital circuits? Start learning about the following topics: gates, flip-flops, shift registers, counters, adders, subtractors, multiplexers, demultiplexers, priority encoders, encoders, decoders, K-maps, boolean algebra, and De-law. Morgan's Is that all? Nope. state machines as well They form the nucleus of the design cycle.

Best references Digital Circuit :

Morris, M. digital design by Mano. You will find clear foundation in this text. You won't struggle to understand it here.

Digital Design Team at Wakerly (Pearson publication). You can acquire sophisticated digital design methods from this book.

CMOS VLSI Design by Neil Weste and David Harris Without missing a word, give the third chapter your undivided attention. maximise the depth of your comprehension. at the very least, the construction of hardware gates and flops.

Now that you've developed a digital circuit in your brain. You understand how nanoscale technology functions and how electrical impulses go from one spot to another in a finite amount of time (3rd reference in the digital circuit). Let's go on to a thorough examination of Verilog.

Best References Verilog HDL :

Verilog by Samir Palnitkar. Beginners can easily understand this text. You don't dream about actual use. It can be used to create the necessary codes for logic circuits (synthesize-able). citations for digital design Examine it to see what you are able to write.

Award-Winning Verilog & System by Cliff Cummings Papers on Verilog is a source that is cited. Consider the following quotation to be holy Verilog. Read Verilog's documentation slowly. It's gratuitous. Use this reference if you are familiar with the words timing, power, and optimization in digital circuits.

Not all codes will result in digital circuits that can be used practically. You must be familiar with each keyword's usage. In Verilog, some keywords are created solely for simulation purposes; they don't produce any logic circuits.

Never, ever attempt Discover something new on Asicworld.com. Use it only for syntax.

Never, ever, ever believe any code you find online. It's terrible. You'll understand it afterwards. It prevents anyone from growing as a result.

Having trouble learning some subjects? Try to use prominent university names in the search field. comparable to "Stanford studies digital design." Materials are created by researchers and clever people worldwide. It will enchant you.

Try to familiarise yourself with tools like ModelSim, Xilinx Vivado, and Microsemi Libero. Everyone has been set free. I wholeheartedly support Vivado.

Some suggestions suggest reading up on static timing analysis, critical pathways, and data paths. That, however, is not a part of Verilog HDL. They are all engaged in the creation of semiconductors, which uses analysis tools.

robust typing is a VHDL term. Beginners will find it more challenging to make mistakes because the compiler will stop you from creating bad code. In Verilog, weak typing is employed. You can write shorter, but inaccurate, code thanks to it.

Verilog is more like a programming language than C. Because of this, someone who is knowledgeable in C will have an easier time reading and understanding Verilog's operations.

Using VHDL involves a lot of typing. For the same task, Verilog often utilises less code.

VHDL is very deterministic, in contrast to Verilog, which can occasionally be non-deterministic.

None of these, however, are more significant than the others. You should learn Verilog or VHDL depending on which one you are more likely to use at business or in education. 

If your university uses Verilog, great! If nearby companies that you might wish to work for use VHDL, learn it! The people who use VHDL and Verilog depend greatly on where in the world you are. By entering VHDL vs. Verilog into Google Trends, you may start to receive a pretty clear indicator of which language you should be learning first.

The picture up above contains a lot of intriguing elements. The first is that VHDL and Verilog have both received about the same amount of queries on Google over the past year. This suggests that individuals who are interested in learning more about them find the two to be almost equally popular. I also saw a substantial reduction soon before Christmas, which is worthy of noting.and the New Year. I can only assume that people aren't searching for their HDL problems on Google during this time because they aren't at work or school.

In India and the US, where VHDL and Verilog appear to be almost equally popular, Google searches are most common. Verilog is slightly more popular than VHDL in the US. I am aware from personal experience that the US business sector favours Verilog whereas the defence sector typically favours VHDL. You'll observe that in Germany and France, VHDL is much more widely used than Verilog. If you are from either of these two countries, I would strongly recommend learning VHDL first! Establish your priorities because Verilog is unquestionably more popular than VHDL in China and South Korea.

Conclusion:

Verilog is an HDL used to model electronic systems, whereas VHDL is an HDL used in electronic design automation to specify digital and mixed-signal systems such as field programmable gate arrays and integrated circuits.

[contentone3]

SERDES Interface- PHY with PIPE Interface-ASIC/SoC Physical Design-SoCs for Edge Computing

PHY with PIPE interface Multi-chipset designs execute ASICs and other incorporated items across various bites the dust inside a solitary bundle. The ODSA bunch expects to characterize an open consistent connection point to such an extent that chiplets from different sellers can be created to shape space explicit gas pedals. As a piece of this work, the ODSA studied and investigated a wide scope of new between chipset PHY advancements. This paper reports the aftereffects of the overview. We foster a system to assess these PHY advancements. In view of our investigation, we propose the utilization of a deliberation layer with the goal that numerous PHY innovations can introduce a typical connection point. Fringe Component Interconnect (PCI) Express is a cutting edge, elite execution, highlight point, broadly useful info yield interconnect correspondence convention. PCI Express overrides other heritage transports and gives higher data transmission which settles on it an optimal decision for some applications. It gives a layered design that contains three separate layers. Multichiplet framework in-bundle designs certainly stand out as an instrument to battle high SoC configuration costs and to monetarily fabricate huge ASICs. These designs require low-power region effective off-pass on-bundle pass on to-pass on correspondence. Current innovations either stretch out on-pass on high-wire count transports utilizing silicon interposers or off-bundle sequential transports. The previous methodology prompts costly bundling. The last option prompts perplexing and high-power designs. We propose a straightforward bundle of-wires interface that joins simplicity of advancement with minimal expense bundling methods. We foster the point of interaction and show how it tends to be utilized in multi chipset frameworks. The RTL of PCI Express Gen5.0 is planned in SystemVerilog language and for the check reason, the approach utilized is Universal Verification Methodology. Reproduction results show the adequacy of the proposed methodology which is displayed in the Synopsys Discovery Visual Environment apparatus effectively.

serialize-and-deserialize (SerDes) fast information grouping. The generally utilized current-mode rationale (CML) designs of hook and multiplexer/demultiplexer (MUX/DEMUX) are supplanted by the proposed TC way to deal with permit more headroom and to bring down the power utilization. Through the stacked transformer, the information clock pulls down the differential source voltage of the TC lock and the TC multiplexer center while switching back and forth between the two-stage tasks. With the upgraded channel source voltage, the TC configuration draws in more channel current with a less width-to-length proportion of NMOS than that of the CML partner. The source-offset voltage is diminished so the stock voltage can be decreased. The lower supply voltage further develops the power utilization and works with the joining with the low voltage supply SerDes interface. The MUX and the DEMUX chips are created in a 65-nm standard CMOS process and work at 0.7-V stock voltage. One potential arrangement distinguished is the sequential connection point, likewise named as SERDES (Serializer/DESerializer) interface. A run-of-the-mill SERDES interface contains encoder/decoder, PLL, timing-control, and multiplexer/de-multiplexer. Encoding of sequential information tackles rapid sequential information transmission issues by consolidating clock installing, DC adjusting, sync data addition, and mistake recognition. DC adjusting additionally addresses the issue of Inter-Symbol Interference (ISI). Accessible SERDES interface gadgets have constraints like unfortunate decrease factor, no clock inserting, or non-accessibility of the space-qualified parts. Thus, an endeavor is made to comprehend and carry out this connection point with the objective of native SERDES ASIC advancement, which will likewise defeat the above issues. Different sequential encoding methods are reviewed and an 8B/10B encoding procedure is finished for exceptionally rapid sequential information transmission. As an underlying advance, an 8B/10B encoding-based SERDES connection point is executed in an FPGA.

 ASIC/SoC Physical Design A superior ASIC/SOC plan procedure for fast plan intermingling is portrayed in this paper. Dissimilar to the regular ASIC/SOC plan systems zeroed in on mechanization, our new technique centers around smoothing out the ASIC/SOC stream's planning-consuming strides by applying our master's BKMs to speed up plan combination. It empowered us to abbreviate the tedious stages significantly with moderately negligible exertion. This paper depicts the philosophy utilized by the IBM Microelectronics Division for the plan of its Blue Logic® application-explicit coordinated circuits (ASICs) and framework on-a-chip (SoC) plans. This philosophy is utilized by both IBM ASIC and SoC originators, as well as OEM clients. A critical focal point of the IBM ASIC/SoC approach, laid out in the primary part of this paper, is the initial time-right techniques for planning and checking that augment the right activity of the chip upon item combination. The second part of this paper portrays progress in an approach that arrangement with the actual impacts of contracting gadget calculations and empower configuration utilizing the exhibition and thickness abilities accessible in the new innovations, and strategic advances that have further developed plan completion time (TAT) for huge, complex plans. One variable for this development is that wire delays are expanding as a level of generally process duration. Thus, arrangement necessities to think about something beyond the productivity of the last plan. The position is presently a significant supporter of timing conclusion results. The issue space for the position currently covers a wide scope of configuration styles, including ASIC, SOC, and Microprocessor. Each of these acquaints remarkable difficulties with arrangement calculations. Likewise, the capacity of the situation calculations to work steadily inside a planning conclusion framework is developing inconsequentiality. -

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[networkeducative]

Top Interview Questions of Network Engineer

Top Interview Questions of Network Engineer

1) What is the first product of the Cisco ?

In the year of 1985 the cisco company sold it first product and that first product was "Network Interface Card" that NIC cards for the digital equipment corporation's computer.

2) What is networking ?

Networking is defined as the "connectivity of two or more devices so that they can communicate with each other".

3) Why we need networking ?

Following are the reasons of we need networking :

Information sharing

File Sharing

Resource Sharing

4) What is difference between the 568A and 568B ?

568B is the standard of ethernet cable for the different types of devices. Here below is the sequence of colors wires of the 568B standard:

Light Orange                   tx+

Orange                             tx-

Light Green                     Rx+

Blue                                 unused

Light Blue                       unused

Green                               Rx-

Light Brown                    unused

Brown                              unused

568A is the standard in which the sequence of the colors wires:

Light Green                     tx+

Green                               tx-

Light Orange                   Rx+

Blue                                 unused

Light Blue                       unused

Orange                             Rx-

Light Brown                    unused

Brown                              unused

5) What is the bandwidth of the 1000BASE-T and IEEE name ?

The bandwidth of this 1000BASE-T is 1000 Mbps and the IEEE name is 802.3ab.

6) What are the five vendors of networking Devices ?

Following are the vendors of the networking devices :

Cisco

Huawei

Juniper

HP

Dell

7) In which year OSI model was released ?

In 1984 International Organization for standardization published the Open System Interconnection model.

8) What are the responsibilities of the application layer ?

Following are the responsibilities of the application layer :

It deals with the presentation of the data.

Encoding-Decoding

Encryption-Decryption

Compression-Decompression

9) What is the session ID ?

Session id is the id that is used for identification of session between source and the destination.

10) What is FTP ?

FTP stands for the file transfer protocol which is use for the transferring of files form one computer to an other computer and ftp allow access to files and also access to directories. FTP is the slow protocol because of the TCP.

11) What is SNMP ?

SNMP stands for the simple network management protocol and it is used for enabling the central management of network. Simple network management protocol work with the TCP/IP and it uses the UDP for the transportation of the data.

12) What are the major functions of the transport layer ?

Transport layer is used for the identification of the service.

Transport layer is used for the multiplexing and demultiplexing.

Transport layer is used for the segmentation.

Transport layer is used for the sequencing and reassembling.

Transport layer is used for the error correction and flow control.

13) What is the value of the MTU ?

MTU stands for the maximum transmission unit and the value of MTU is 1500 bytes.

14) What is difference between routing protocols and routed protocols ?

Routing Protocol

are the protocols that are used for the path determination.eg: OSPF, EIGRP, ISIS

Routed Protocols

are the protocols that are used as a data carrier.eg: IP, IPX, AppleTalk

15) What is the range of the multicasting address in IPv4 ?

The range of the multicasting address in IPv4 is 224-239.

16) Who is responsible for the global coordination of the internet protocol addressing system ?

Internet Assigned Name And Authority (IANA).

17) What are the layers that are responsible for the data flow ?

Following are the layers that are responsible for the data flow in a network:

Physical Layer

Datalink Layer

Network Layer

18) What are the types of the transmission ?

There are the three types of transmission:

Unicast            one to one

Multicast         one to specific group

Broadcast        one to everyone

19) Is switch a unicast device ?

Switch is the broadcasting device and it is the broadcasting device till the time its switching table not complete and when it's table complete it become the unicasting device.

20) What is the CAPWAP tunnel ?

CAPWAP is stands for the control and provisioning of wireless access point CAPWAP tunnel is the tunnel which is create between the controller and the light weight access point.

21) What is the NIC ?

NIC stands for the network interface card it is card that is company install in the device without this card we don't able to connect to the internet.

22) Convert 200.100.150.100 address into the binary form ?

11001000.01100100.10010110.01100100

23) What are the OSPF special area types ?

Backbone Area

Area 0 is the backbone area.

Non-Backbone Area

Others areas types are following :

Stub Area

Totally Stub Area

NSSA (Not so stubby area)

Totally NSSA

24) What is the AD value of ISIS and what is the preference  value of ISIS ?

The AD value of ISIS is 115

and the AD value in Huawei is called the preference the preference value of ISIS is 15

25) What are the features of ISIS ?

Following are the features of ISIS protocol that stands for intermediate system to intermediate system:

Designed for the large scale network.

ISIS convergence time is very fast.

Support the classful and classless Routing

Easy to configure than the Open Shortest Path First.

26) What are the backbone router in ISIS ?

Level 2 router in the ISIS is known as the backbone router. It create the level 2 link state database.

27) Routing is done on the basis of destination address if we want to do routing on the basis of source address what should we do ?

If we want to do routing on the basis of the source address we should have to do the policy based routing and policy based routing will be done with the help of the access list/prefix list.

28) How many VLANs exist by default ?

VLAN 1: It is the VALN that active by default all the ports are the members of this.

VLAN 1002: It is the VALN that active by default and it is used for the fddi-default.

VLAN 1003: It is the VALN that active by default and it is used for the token-ring-default.

VLAN 1004: It is the VALN that active by default and it is used for the fddinet-default.

VALN 1005: It is the VALN that active by default and it is used for the trnet-default.

29) What is autonomous system ?

Autonomous system is the large network that is the collection of the multiple network.

30) What is administrative value of EBGP and IBGP ?

The administrative value of EBGP is 20.The administrative value of IBGP is 200.